ARM 7 Tutorial - Part 2
- Processor Modes determines which registers are active. They are used to define various kinds of registers, their visibility and rights to modify CPSR register.
- Each processor modes may be either- Privileged or Non-Privileged.
- Privileged Mode has full read write access to the CPSR.
- Non-Privileged Mode has only read access to control field CPSR, but read/write access to condition flags.
ARM has 7 different modes which come under Privileged and Non-privileged Modes. They are-
- Abort Mode
- Fast Interrupt Mode
- Interrupt Request Mode
- Supervisor Mode
- System Mode
- Undefined Mode
- User Mode
Abort Mode is a mode, when there is a failed attempt to access memory.
Fast Interrupt request and Interrupt request Mode
These correspond to interrupt levels available on ARM. Fast Interrupt Request (FIQ) supports high speed interrupt handling. Interrupt Request (IRQ) supports, all other interrupt sources in a system.
It is a state in which a processor goes after RESET. Generally, it is a mode in which OS Kernal executes. This is because when a processor is RESET the first thing that it is expected to execute is its OS codes and not the user applications.
Special Version of User Mode, that allows full read\write access to CPSR. It is also targeted for supervisory applications.
Processor Enters Undefined Mode when it encounters an undefined instruction. Example: - illegal opcodes
User Mode is used by program and applications. It is used to run the application codes. Once in user mode, the CPSR cannot be written to and modes can only be changed when an exception is generated.
Figure below shows Modes and Associated Registers
- ARM has 37 registers in all.
- 20 registers are hidden from program at different times. These registers are called banked registers.
- Banked registers become available, when processor is in particular mode.
- The user registers R0-R7 are common to all operating modes.
- FIQ mode has its own R8-R14 that replace the user registers.
- Each of the other modes have their own R13 and R14.
- CPSR is common to all modes and there is an additional Saved program Status register (SPSR)
If processor goes to some other modes from user mode, example user mode to FIQ mode, FIQ has bank registers from R8 to R14. So effectively a fresh copy of R8 to R14 is made available in FIQ mode. When mode change takes place, content of CPSR will be saved to SPSR. When returned back, content of SPSR will be loaded back to CPSR.
ARM Memory organization and Data Types
- ARM can be configured as Little Endian or as Big Endian.
- Addresses are for each byte.
- Data word is 32 bit long.
- Word divided into 4 bytes of 8 bit each.
- Address is also 32 bit long.
- Addresses refers to byte ( Address 4 starts at byte 4)
ARM INSTRUCTION SET
- Instruction processes data in registers.
- Memory is accessed by load and store instructions.
Classes of instructions are-
- Data processing instructions
- Branch Instructions
- Load- Store instructions
- Software interrupt instructions
- Program Status Register Instructions
The Instruction set will be discussed in next tutorial in detail.
Happy learning !!!