ARM 7 Tutorial - Part 3

Data Processing Instructions

The general form for all Data Processing Instruction is shown below

 

 

  • Each Instruction has a result register and 2 Operands.
  • First Operand must be a register, but second can be a register or an immediate value.
  • 32 bit shift is provided by barrel shifter which shifts the second operand by 32 bits within instruction cycle.
  • S, SETS S flag. This affects CPSR.

ARM 7 - Data Processing Instructions

 

Data is manipulated within registers. Various instructions are-

  • Move Instructions
  • Arithmetic Instructions - Including Multiply Instructions
  • Logical Instructions
  • Comparison Instruction

 

Suffix S on these Instructions updates flags in CPSR. Thus conditional flags will be set appropriately. (When S is not added flags will not be updated)

 

1. MOVE INSTRUCTIONS

  • MOV Rd,N
    • Rd: Destination Register
    • N: Immediate Value or source register
    • E.g.: MOV r7, r5
  • MVN Rd,N
    • Result in Rd will be NOT of 32 bit value of the source.
  • MOV r7,r5,LSL#2 (Barrel Shifted)
    • Multiplies the content in r5with 4 and puts the value in r7 i.e. r7= [r5]x4

 

2. ARITHEMETIC INSTRUCTIONS

 

  • Simple Arithmetic Instructions implements 32 bit addition and subtraction.
  • It employs 3 operands, 2 sources and a Destination.
  • SUB r0,r1,r2
    • Subtract value stored in r2 from that of r1and store in r0.
  • SUBS r1,r1,#1
    • Subtract 1 from r1 and store result in r1 and update Z and C flags.

 

Use of Barrel Shifter with Arithmetic and Logical Instructions increases the set of possible available operations.

  • ADD r0,r1,r1 LSL #1
    • Register r1 is shifted left by 1, (i.e. multiplied by 2), then it is added with r1 and the result is stored in r0.

 

I. Multiply Instructions

  • Multiplies contents of a pair of registers.
  • Long Multiply generates 64 bit results.

 

  • MUL r0.r1,r2
    • Contents of r1 and r2 are multiplied and the result is put in r0.

 

  • UMULL r0,r1,r2,r3
    • Unsigned Multiply with results stored in r0 and r1. This is the case of a long unsigned multiplication.

 

II. Multiply and Accumulate Instructions

  • Results of multiplication can be accumulated with the content of another register.

 

  • MLA Rd,Rm,Rs,Rn
    • Rd= (Rm x Rs)+ Rn

 

  • UMLAL RdL,RdH,Rm,Rs
    • [RdH,RdL]= [RdH,RdL]+(Rm+Rs)

 

3. LOGICAL INSTRUCTIONS

  • Bit wise logical operation on 2 source registers.
  • Has 2 source registers and 1 destination register.
  • Operations possible- AND , OR, EX-OR, Bit Clear, ORR etc

 

  • AND r0,r1,r2 => r0=(r1&r2)

 

  • BIC r0,r1,r2 [ Bit Clear]
    • r2 contains a binary pattern, where every binary 1 in r2 clears a corresponding bit location in r1.

 

4. COMPARE INSTRUCTIONS

  • Enables comparison of 32 bit value.
  • Updates CPSR flags, but do not affect other registers.

 

Simple Compare

  • CMP r0,r9
    • Flags sets as a result of r0-r9

 

Test for Equality

  • TEQ r0,r9
    • Flags sets as a result of r0 EX-OR r9.

 

Test

  • TST r0,r9
    • Flags sets as a result of r0 AND r9.

 

Load and Store Instructions

Transfers data between memory and processor registers. They are of 3 types-

  • Single Register Transfer
  • Multiple Register Transfer
  • Swap Instructions

 

1. SINGLE REGISTER TRANSFER

  • Data types supported are signed and unsigned words (32 bits), half words, bytes.
  • Load Instructions
    • LDR – word (32 bits boundary)
    • LDRH- Half word (16 bit boundary)
    • LDRB- byte
  • Store Instructions
    • STR, STRH, STRB

 

E.g.:- LDR r0, [r1]

 

2. MULTPLE REGISTER TRANSFER

  • Transfers Multiple Registers between memory and Processor in a single instruction.
  • More efficient for moving blocks and memory.
  • These instructions increase interrupt latency.
  • Mnemonics used are – LDM (Load), SDM (store)

 

3. SWAP INSTRUCTIONS

  • Special case of Load and Store Instructions.
  • Instructions are-
    • SWP: swap a word between memory and register
    • SWPB: swap a byte.

Control Flow Instructions

  • Branch and Conditional Branch
  • Conditional Execution
  • Branch and Link Instructions
  • Subroutine return Instructions

 

1. BRANCH AND CONDITIONAL BRANCH INSTRUCTIONS

Branch Instruction has got 2 Variant

  • Branch - B label : E.g.- B forward
  • Conditional Branch - B<cond> label: E.g.- BNE loop (Conditions will be discussed later)

 

2. CONDITIONAL EXECUITION

Every instruction in ARM can be executed with respect to certain conditions.

E.g.: ADDEQ r0,r1,r2

 Advantages-

  • Reduces number of Branches
  • Increases Code density 

The table below shows various conditional codes that can be added as suffix to all instructions in ARM.

Condition Code Summary

 

ARM 7 - Condition Code Summary

 

Eg: - ADDEQ r0,r1,r2

This instruction will only be executed when zero flag is set.

 

3. BRANCH AND LINK INSTRUCTIONS

  • Used for subroutine call.
  • While Branching, saves the address following the branch in link register.
  • E.g.- BL Subroutine

 

4. SUBROUTINE RETURN INSTRUCTIONS

  • There are no specific instructions for RETURN from subroutine.
  • To return from subroutine, the value in link register has to be moved to Program counter, at the end of execution of subroutine.

 E.g. - subroutine : --------------------

                            --------------------

                            MOV PC, r14

 

Co-Processor Instructions

  • Used to Extend Instruction set
  • Instructions used

CDP- Coprocessor Data processing

LDC- Load Coprocessor from Memory

 

These are the basics of ARM, especially ARM 7 processor. LPC 21XX, is on of the microcontroller build upon an ARM 7 TDMI core. Further details of LPC 21XX is available in its data sheet. I am concluding the Tutorial Series on the basics of ARM processor. Thank you for your cooperation. 

 

Link for LPC 21XX data sheet:-

http://www.datasheetarchive.com/download/?url=http%3A%2F%2Fwww.datasheetarchive.com%2Fpdf%2FDatasheet-028%2FDSA00502688.pdf

 

 

Happy Learning!

 

HARI

[email protected]

www.haripanangad.co.cc